I-C structures of the general character referred to above are conventionally produced by epitaxial growth, starting from a monocrystalline silicon substrate, with suitable doping of selected portions of both the substrate and the epitaxial stratum. With a substrate of P-type conductivity, for example, a bipolar NPN transistor can be formed in this way by using a buried layer of N-type conductivity in the substrate as the collector, a P-type base layer embedded in the N-doped epitaxial stratum as a base, and an N-type layer embedded in the P-type base layer as an emitter; such a structure has been described and illustrated in commly owned U.S. patent application Ser. No. 99,897 filed 12-3-79 by one of us, Franco Bertotti, jointly with six others. The epitaxial stratum is generally subdivided into several sections by zones of the opposite conductivity type (P in this instance) forming barrier junctions designed to separate different semiconductor components from one another.
For economic reasons it is desirable to design the various components of a silicon wafer in such a way that, even though they may be of mutually different character, at least some of their constituent layers can be formed concurrently in the epitaxial stratum by the introduction of impurities through overlying masking layers. With this technique it is possible, in principle, to form a bipolar NPN transistor simultaneously with a J-FET of the N-channel type having a gate electrode connected to the substrate (which is usually grounded). When it is desired to convert such a J-FET into a resistor by conductively interconnecting its gate and source electrodes, the grounding of its gate is often an inconvenience especially when these electrodes are to be connected to those of other components. Moreover, it is difficult to design a field-effect transistor of this description with a pinch-off voltage below 10 V. One could also produce a P-channel FET in the wafer concurrently with a vertical NPN bipolar transistor by forming its channel simultaneously with the base layer of the latter; on account of the large amount of doping required for the base layer, however, this would lead to an undesirably high pinch-off voltage for the FET unless its P-channel were doped independently, e.g. via ion implantation, with resulting increase in cost.